A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store at least one data bit. Such memories include volatile and nonvolatile memories. Volatile memories require power in order to retain stored data, while nonvolatile memories retain their stored data even after power is removed.
Certain types of nonvolatile memory, such as NAND flash memories, utilize memory cells that are implemented as respective floating gate transistors. Such transistors include both a control gate and a floating gate. Depending on the amount of electric charge on its floating gate, the transistor exhibits a certain threshold voltage (Vt). The corresponding memory cell can therefore be written with data by controlling the amount of charge on the floating gate. To read stored data from the memory cell, a reference voltage (Vref) is applied to the control gate. If Vref is higher than Vt, the transistor is turned on, and otherwise the transistor is turned off. Accordingly, the data stored in the cell can be readily detected by sensing current flow between source and drain terminals of the transistor, typically using a sense amplifier.
In single-level cell (SLC) flash memory, each memory cell stores only one bit of data. Upon readout, for example, those cells having Vt values below Vref may be assumed to store a “1” bit and those having Vt values above Vref may be assumed to store a “0” bit. Due to noise and other variations in the memory array, not all of the memory cells that store bits at a particular logic level will have exactly the same Vt value. Instead, the actual Vt values associated with a given logic level over a group of the memory cells will tend to follow a distribution, such as, for example, a Gaussian distribution. Therefore, in order to read the stored bits from the respective memory cells, the reference voltage Vref may be placed approximately midway between the means of the two different Vt distributions. As noted above, when Vref is applied to the control gates of the memory cell transistors, the transistors having a Vt value lower than Vref will be turned on, indicating storage of a “1” bit in each of the corresponding cells, while the transistors having a Vt value higher than Vref will be turned off, indicating storage of a “0” bit in each of the corresponding cells.
In multi-level cell (MLC) flash memory, each memory cell is able to store multiple bits of data, such as two bits of data in the case of a two-level memory cell, three bits of data in the case of a three-level memory cell, and so on. Thus, for example, in the case of a two-level memory cell storing two bits of data, four different Vt distributions characterize the four different possible combinations of two bits that may be stored in that cell. Each such Vt distribution is associated with a different Vt level. The possible bit combinations are generally mapped to the Vt levels using a Gray code, such that a change from one Vt level to its neighboring Vt level leads to a change in only one bit position.
Reading out stored data from such multi-level cells involves using multiple reference voltages. For example, in the two-level memory cell case, three different reference voltages are used, arranged between the four different Vt levels. Determining the data stored in a given cell may also involve the use of soft read operations, each comprising multiple hard read operations using a different reference voltage.
However, conventional soft read operations can require an excessive number of hard read operations. As a result, soft read latency is increased, thereby degrading memory access time performance. In conventional practice, therefore, a significant performance penalty is typically associated with performance of soft read operations.